1. Field of the Invention
The present invention relates generally to semiconductor packages and, more particularly, to a semiconductor package which includes offset etched corner leads to allow etching beyond a minimum capable distance between the die pad tie bars and adjacent lands, or leads which are etched in a manner allowing for an increase in the size of the die pad.
2. Description of the Related Art
The current trend in the electronics industry is to provide electronic devices which are multi-functional, compact, and capable of achieving high performance levels. In view of this trend, a requirement has arisen that the semiconductor packages which are used in such electronic devices be made in a “chip size”. These chip-size semiconductor packages are usable in portable products such as cellular phones and PDA's which require high levels of reliability, electrical efficiency, and a small or compact size of minimal weight.
Chip-size semiconductor packages as currently known in the electrical arts typically include a leadframe, and are fabricated in a manner wherein a plurality of input/output signal lands are formed at the peripheral edge of the bottom surface of the package. The package is electrically connected to an underlying substrate such as a printed circuit board (PCB) by soldering the lands on the bottom surface of the package to corresponding pads of the board. In addition to including leads which define the signal lands at the periphery of the bottom surface of the package, the leadframe also includes a semiconductor mounting paddle or pad, the bottom surface of which is also exposed within the package for purposes of maximizing an emission rate of heat generated by the semiconductor die mounted to the top surface thereof.
Internal to such semiconductor package is a semiconductor die having a multitude of input/output pads or terminals. Such terminals are in turn electrically connected to respective leads of the leadframe which, as indicated above, define respective ones of the signal lands. In an often used methodology for fabricating a plurality of the above-described semiconductor packages, a matrix of interconnected leadframes are etched into a leadframe strip. Subsequent to the attachment of the semiconductor dies to respective ones of the die pads and electrical connection of the terminals of the dies to respective ones of the leads, an encapsulation step facilitates the application of an encapsulant material onto the surface of the leadframe strip to which the dies are attached. This encapsulation step covers the dies, the side surfaces of the die pads, and portions of the leads within a single block of encapsulant material. The encapsulant material is then hardened, with a cutting step thereafter being used to separate individual semiconductor packages from each other and from the disposable portions of each of the leadframes within the leadframe strip. The cutting step severs the connection between each of the interconnected leadframes within the leadframe strip, and the die pad and leads of each individual leadframe. This cutting or “singulation” process is typically accomplished through either a sawing process (saw singulation) or a punching process (punch singulation). The formation of the individual leadframes within the leadframe strip is itself typically accomplished through either a chemical etching or mechanical stamping process.
An overall limitation of the design of the above-described semiconductor package pertains to the electrical connections and configurations utilized to satisfy the required electrical inputs and outputs to and from the input/output terminals of the semiconductor die. In this regard, the satisfaction of current functionality requirements typically necessitates the highest possible lead count for the semiconductor package. Those leads of each leadframe disposed adjacent to the tie bar(s) extending to the die pad are typically referred to as corner leads, and are those which are typically the least reliable due to their reduced land length attributable to the required spatial separation between such corner leads and the corresponding tie bar. The present invention addresses this reliability issue by providing a leadframe which includes purposely offset etched corner leads which allow for etching beyond a minimum capable distance between the tie bar and those corner leads adjacent thereto. The resultant added length to the lands defined by these corner leads provides a highest lead count semiconductor package with better board level reliability attributable to longer land lengths.